module switch(
        input           CLK_I,
        input           RST_I,
        input           CYC_I,
        input           STB_I,
        output          ACK_O,
        output  [31:0]  DAT_O,
        input           i_sw0,
        input           i_sw1,
        input           i_sw2,
        input           i_sw3
);

wb_ack u_wb_ack(
        .CLK_I(CLK_I),
        .RST_I(RST_I),
        .CYC_I(CYC_I),
        .STB_I(STB_I),
        .ACK_O(ACK_O)
);

assign  DAT_O = {
        7'b0, i_sw3,
        7'b0, i_sw2,
        7'b0, i_sw1,
        7'b0, i_sw0
};

endmodule
